You are cordially invited to attend the 2000 Symposium on VLSI Circuits, to be held on June 15th - 17th, 2000, at the Hilton Hawaiian Village in Honolulu, Hawaii.
This year the Symposium marks its 14th anniversary. The Symposium has established itself as a major international forum for presenting timely and important new developments in the VLSI and ULSI circuit design community. The scope of the Symposium has traditionally covered Analog, Digital, Memory and Signal Processing circuits contributed from both industry and universities from around the world. Preceding the Symposium on June 14th, a one-day short course on VLSI Circuits will be held. This short course will focus on Circuit Design for Wireline and Optical Fiber Communications. As has been traditional for a number of years, the Symposium on VLSI Circuits will be held for three days following the Symposium on VLSI Technology held at the same location.
The technical program committees reviewed one hundred ninety two (192) papers from nineteen (19) countries around the world. While the technical program is highlighted by very strong papers from universities, we achieved a record this year for industry paper submissions to the Symposium. From the papers submitted, sixty-two (62) papers were selected for presentation. We hope that you agree that these papers disclose new and interesting circuit design concepts for memories, processors, communications circuits, and analog and digital signal processing. We expect the technical content of the program to make the Symposium a worthwhile event for every attendee.
In addition, we have invited four speakers to describe to you areas of interest to VLSI designers; system LSI's for mobile communications, MEMS structures and circuits, addressing ESD for microprocessors and ASICS in the 21st century, and the evolution and revolution of memory technology.
In contrast to these formal talks, we have prepared four evening rump sessions on interesting and provocative subjects that offer you an opportunity to participate in discussions of interest with an international mix.
The symposium web page contain the advance program and forms for registration and hotel accommodations. Please try to complete and return these forms as soon as possible. While on-site registration will be available, early registration will facilitate the Symposium planning.
We look forward to meeting with you at the Symposium in Honolulu.
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David Scott |
Masakazu Yamashina |
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Program Chairman |
Program Co-Chairman |
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SESSION 1 - Tapa II Plenary Session I |
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Thursday, June 15, 8:30 a.m. |
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Chairpersons: |
David Scott, Texas Instruments, |
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8:30 a.m. |
Welcome and Opening Remarks |
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William Bidermann, S3 Inc. |
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8:45 a.m. |
IMT 2000 Terminal and its Requirements for Device Technologies, |
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1.1 |
K. Nagata, NTT Mobil Communications |
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9:30 a.m. |
MEMs Structures and Circuits, |
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1.2 |
K. Najafi, University of Michigan |
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10:15 a.m. |
Break |
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SESSION 2 - Tapa II Sensors and Displays |
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Thursday, June 15, 10:30 a.m. |
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Chairpersons: |
M. Horowitz, Stanford University, |
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10:30 a.m. |
A Monolithic Surface Micromachined Z-Axis Gyroscope with Digital Output, |
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2.1 |
X. Jiang, J. Seeger, M. Kraft* and B. Boser, University of California, Berkeley, CA and *Southampton University, Southampton, United Kingdom |
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10:55 a.m. |
8-Bit/Color 1024x768 Microdisplay with Analog In-Pixel Pulse Width Modulation and Retinal Averaging Offset Correction, |
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2.2 |
T. Blalock, N. Gaddis, K. Nishimura and T. Knotts, Agilent Laboratories, Palo Alto, CA |
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11:20 a.m. |
A Low Power, Low Noise, Ultra-Wide Dynamic Range CMOS Imager with Pixel-Parallel A/D Conversion, |
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2.3 |
L. McIlrath, Massachusetts Institute of Technology, Cambridge, MA |
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11:45 a.m. |
A CMOS Image Sensor for Focal-Plane Low-Power Motion Vector Estimation, |
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2.4 |
D. Handoko, S. Kawahito, Y. Tadokoro*, M. Kumahara* and A. Matsuzawa**, Shizuoka University, Hamamatsu-shi, Japan and *Toyohashi University of Technology, Toyohashi-shi, Japan and **Matsushita Electric Industrial Co. Ltd., Moriguchi-shi, Japan |
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12:10 p.m. |
Lunch |
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SESSION 3 - Tapa II RF Receivers |
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Thursday, June 15, 1:30 p.m. |
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Chairpersons: |
B. Razavi, UCLA, |
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1:30 p.m. |
A Wide-Band Direct Conversion Receiver with On-Chip A/D Converters, |
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3.1 |
A. P ¬ rssinen, J. Jussila, J. Ryyn¬ nen, L. Sumanen, K. Kivek¬ s, K. Halonen, Helsinki University of Technology, Helsinki, Finland |
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1:55 p.m. |
A 5.2-GHz CMOS Receiver with 62-dB Image Rejection, |
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3.2 |
B. Razavi, University of California, Los Angeles, CA |
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2:20 p.m. |
A 2 GHz CMOS Double Conversion Downconverter with Robust Image Rejection Performance Against the Process and Temperature Variations, |
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3.3 |
E. Song, S.-I. Chae and W. Kim, Seoul National University, Seoul, Korea |
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2:45 p.m. |
A Single-Chip 2.4GHz Direct-Conversion CMOS Receiver for Wireless Local Loop Using One-Third Frequency Local Oscillator, |
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3.4 |
K. Lee, J. Park, J.-W. Lee, S.-W. Lee*, H.-K. Huh*, D.-K. Jeong* and W. Kim*, Global Communications Technology, Inc., Los Altos, CA and *Seoul National University, Seoul, Korea |
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3:10 p.m. |
Break |
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SESSION 4 - Tapa III Timing Circuits |
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Thursday, June 15, 1:30 p.m. |
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Chairpersons: |
W. Lee, Texas Instruments, |
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1:30 p.m. |
A CMOS 50% Duty Cycle Repeater Using Complementary Phase Blending, |
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4.1 |
K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa and M. Yotsuyanagi, NEC Corporation, Kanagawa, Japan |
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1:55 p.m. |
A Low Jitter Dual Loop DLL using Multiple VCDLs with a Duty Cycle Corrector, |
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4.2 |
Y.-J. Jung, S.-W. Lee, D. Shim, W. Kim, C.-H. Kim* and S.-I. Cho*, Seoul National University, Seoul, Korea and *Samsung Electronics Co., Korea |
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2:20 p.m. |
On-Chip Picosecond Time Measurement, |
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4.3 |
V. Gutnik and A. Chandrakasan, Massachusetts Institute of Technology, Cambridge, MA |
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2:45 p.m. |
Break |
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SESSION 5 - Tapa II RF Transmitters |
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Thursday, June 15, 3:25 p.m. |
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Chairpersons: |
B. Razavi, UCLA, |
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3:25 p.m. |
A Common-Gate Switched, 0.9W Class-E Power Amplifier with 41% PAE in 0.25 [ m CMOS, |
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5.1 |
C. Yoo and Q. Huang, Swiss Federal Institute of Technology, Zurich, Switzerland |
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3:50 p.m. |
A Translinear-Based Chip For Linear LINC Transmitters, |
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5.2 |
B. Shi and L. Sundstr Ø m, Lund University, Lund, Sweden |
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4:15 p.m. |
A SOI-BiCMOS RF-Transmitter for Personal Digital Cellular Communication (PDC), |
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5.3 |
S. Kishore, G. Chang and C. Hull, Silicon Wave Inc., San Diego, CA |
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4:40 p.m. |
A Si 2-GHz 5-bit LO-Phase-Shifting Downconverter for Adaptive Antennas, |
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5.4 |
T. Yamaji, H. Tanimoto, S. Obayashi and Y. Suzuki, Toshiba Corporation, Kawasaki, Japan |
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SESSION 6 - Tapa III Low Power SRAMs and DRAM DLL's |
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Thursday, June 15, 3:25 p.m. |
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Chairpersons: |
W. K. Loh, Texas Instruments, |
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3:25 p.m. |
A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAMs, |
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6.1 |
K. Agawa, H. Hara, T. Takayanagi and T. Kuroda, Toshiba Corporation, Kawasaki, Japan |
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3:50 p.m. |
A 1.8V 18Mb DDR CMOS SRAM with Power Reduction Techniques, |
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6.2 |
A. Kawasumi, A. Suzuki, H. Hatada, Y. Takeyama, O. Hirabayashi, Y. Kameda, T. Hamano* and N. Otsuka, Toshiba Corp., Yokohama, Japan and *Toshiba Microelectronics Corp., Yokohama, Japan |
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4:15 p.m. |
A 256-Mb Double-Data-Rate SDRAM with a 10-mW Analog DLL Circuit, |
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6.3 |
H. Yahata, Y. Okuda, H. Miyashita, H. Chigasaki*, B. Taruishi*, T. Akiba*, Y. Kawase*, T. Tachibana*, S. Ueda, S. Aoyama, A. Tsukimori, K. Shibata*, M. Horiguchi, Y. Saiki and Y. Nakagome, Hitachi, Ltd., Tokyo, Japan and *Hitachi Device Engineering, Co., Ltd., Chiba, Japan |
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4:40 p.m. |
A Skew and Jitter Suppressed DLL Architecture for High Frequency DDR SDRAMs, |
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6.4 |
T. Hamamoto, S. Kawasaki, K. Furutani, K. Yasuda and Y. Konishi, Mitsubishi Electric Corp., Hyogo, Japan |
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JOINT TECHNOLOGY / CIRCUITS RUMP SESSION Wednesday, June 14 8:00 p.m. - 10:00 p.m. |
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RJ1 |
Circuit and System Technology in the year 2010 |
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Tapa III |
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Organizers/Moderators: |
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Technology: |
Circuits: |
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J. Woo, UCLA |
S. Borkar, Intel |
What kind of systems will be prevailing in the year 2010? Will they be ultra powerful PCs with multi-GHz processors, ultra reality Play Station-X, or ultra intelligent cellular phones? Will high performance chips in such systems integrate 100's of millions (if not billions) of transistors, having feature sizes below 100 nm? Will these systems be monolithic special function chips such as processors, or more likely to integrate diverse functions, towards system-on-a-chip (SOC)? What circuit, device, interconnect, and process technologies will they employ? Technology scaling in the next decade will face even greater challenges. Transistor leakage currents will increase dramatically to satisfy the performance demand. Interconnects will scale to advance integration, but RC delays will start dominating even more. Copper interconnects and low-K dielectrics will ease the burden somewhat, and SOI and derivative silicon technologies will help. But will these advances keep up with the demand? Circuit design, in the presence of high leakage and worse RC's, will be ever more challenging. What will happen to the traditional high performance circuits such as Domino—will they have a future? What will these chips look like in terms of performance, power, and size, and where will these chips get used? If the industry leans towards SOC, then what technology and circuit challenges lay ahead? The panel consisting of technology, circuit, and system experts will discuss these issues, and enlighten us with their thoughts.
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CIRCUITS RUMP SESSIONS Thursday, June 15 8:00 p.m. - 10:00 p.m. |
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R1 |
How to Prosper in a World of Embedded DRAM |
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Honolulu I |
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Organizers: |
P. Gillingham, MOSAID, |
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Moderator: |
B. Prince, Memory Strategies International |
In recent years merged memory and logic processes offering the bit density of commodity DRAM with the transistor performance of pure logic process have become available. With few exceptions, the volume of products employing merged DRAM and logic processes today has fallen well below analysts expectations. What process technology offers the best mix of performance, density and cost for embedded DRAM applications? Is functionality different from stand alone DRAM required? What are the alternatives to monolithic solutions?
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R2 |
Are Analog CMOS Technologies Near Extinction? |
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Honolulu II |
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Organizers/Moderators: |
B. Razavi, UCLA, |
The design of high-performance analog circuits in digital CMOS technologies continues to pose difficult challenges. Will analog CMOS technologies eventually become extinct or will a technology divergence similar to that between memories and microprocessors occur between analog and digital circuits? If a divergence indeed occurs, how different will the two technologies be? Do the additional development time and production costs justify the use of analog technologies? What will the interface between analog and digital circuits look like? Will clever circuit and device techniques obviate the need for custom analog components?
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R3 |
Package Modeling: Or Silicon in System Debug? |
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Honolulu III |
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Organizers: |
B. Gieseke, AMD, |
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Moderators: |
G. Taylor, Intel, |
With package pin counts, I/O bit rates, and dynamic current loads rapidly increasing, there is a perception among many in the design community that signal and supply integrity issues are becoming more serious and more prevalent requiring significant system debug in the lab. It has been suggested that the weak link in the total system design space is the lack of adequate package models where silicon and board modeling are solved problems. The panel will explore these perceptions in light of past successes and failures. Topics which the panel would like to discuss include:
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SESSION 7 - Tapa II Plenary Session II |
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Friday, June 16, 8:30 a.m. |
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Chairpersons: |
David Scott, Texas Instruments, |
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8:30 a.m. |
Addressing ESD for Microprocessors and ASICs in 21st Century Technologies, |
7.1 |
A. Amerasekera, Texas Instruments |
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9:15 a.m. |
Where Does Memory Go in the 21st Century? (Evolution and Revolution of Memory Technology), |
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7.2 |
C.-G. Hwang, Samsung Electronics Co., Ltd. |
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10:00 a.m. |
Break |
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SESSION 8 - Tapa II Wireless Building Blocks I |
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Friday, June 16, 10:20 a.m. |
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Chairpersons: |
G. Nasserbakht, Proxim, Inc., |
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10:20 a.m. |
A 2 dB NF, Fully Differential, Variable Gain, 900 MHz CMOS LNA, |
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8.1 |
E. Sacchi, I. Bietti, F. Gatta*, F. Svelto** and R. Castello*, STMicroelectronics, Pavia, Italy, *University of Pavia, Pavia, Italy and **University of Bergamo, Dalmine, Italy |
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10:45 a.m. |
Sub 1-V 5-GHz-Band Up- and Down-Conversion Mixer Cores in 0.35- mm CMOS, |
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8.2 |
T. Wakimoto, T. Hatano, C. Yamaguchi, H. Morimura and S. Konaka, NTT Lifestyle and Environmental Technology Laboratories, Kanagawa, Japan |
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11:10 a.m. |
A 25.9-GHz Voltage-Controlled Oscillator Fabricated in a CMOS Process, |
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8.3 |
C.-M. Hung, L. Shi*, I. Lagnado**, K. O, University of Florida, Gainesville, FL and *IBM T.J. Watson Research Center, Yorktown Heights, NY and **SPAWAR Systems Center, San Diego, CA |
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11:35 a.m. |
Analysis and Design of Silicon Bipolar Distributed Oscillators, |
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8.4 |
A. Hajimiri and H. Wu, California Institute of Technology, Pasadena, CA |
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12:00 p.m. |
Lunch |
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SESSION 9 - Tapa III DRAMs |
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Friday, June 16, 10:20 a.m. |
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Chairpersons: |
P. Gillingham, MOSAID, |
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10:20 a.m. |
A Next Generation Channeled-DRAM Architecture with Direct Background-Operation and Delayed Channel-Replacement Techniques, |
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9.1 |
Y. Yabe, N. Nakamura, Y. Aimoto, M. Motomura, Y. Matsui and Y. Asakura, NEC Corporation, Kanagawa, Japan |
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10:45 a.m. |
A 2.5V, 2.0Gbyte/s 288M Packet-Based DRAM with Enhanced Cell Efficiency and Noise Immunity, |
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9.2 |
K.-H. Kyung, H.-C. Lee, K.-W. Song, H.-S. Song, K.-W. Jung, D.-Y. Lee, C. Kim and S.-I. Cho, Samsung Electronics, Co. Ltd., Kyungki-do, Korea |
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11:10 a.m. |
A DDR/SDR-Compatible SDRAM Design with a Three-Size Flexible Column Redundancy, |
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9.3 |
T. Sakata, S. Morita*, O. Nagashima, H. Noda, T. Takahashi*, T. Sonoda*, H. Tadokoro*, H. Ichikawa, T. Adou, S. Hanzawa, M. Ohi, S. Ookuma, Y. Suzuki*, H. Tanaka* and K. Ishii, Hitachi Ltd., Tokyo, Japan and *Hitachi ULSI Systems Corp., Tokyo, Japan |
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11:35 a.m. |
CMOS-Logic-Circuit-Compatible DRAM Circuit Designs for Wide-Voltage and Wide-Temperature-Range Applications, |
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9.4 |
H. Mizuno, N. Oodaira*, Y. Kanno, T. Sakata and T. Watanabe, Hitachi, Ltd., Tokyo, Japan and *Hitachi ULSI Systems Co., Tokyo, Japan |
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12:00 p.m. |
Lunch |
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SESSION 10 - Tapa I High Speed Communications I |
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Friday, June 16, 1:30 p.m. |
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Chairpersons: |
M. Horowitz, Stanford University, |
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1:30 p.m. |
Adaptive Bandwidth DLLs and PLLs Using Regulated Supply CMOS Buffers, |
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10.1 |
S. Sidiropoulos, D. Liu*, J. Kim* G. Wei* and M. Horowitz* Rambus Inc., Mountain View, CA and *Stanford University, Stanford, CA |
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1:55 p.m. |
1.6 Gb/s/pin 4-PAM Signaling and Circuits for a Multi-Drop Bus, |
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10.2 |
J. Zerbe, P. Chau, C. Werner, T. Thrush, D. Perino, B. Garlepp*, K. Donnelly, Rambus Inc, Mountain View, CA and *Silicon Labs, Austin, TX |
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2:20 p.m. |
Sub-Picosecond Jitter SiGe BiCMOS Transmit and Receive PLLs for 12.5Gbaud Serial Data Communication, |
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10.3 |
D. Friedman, M. Meghelli, B. Parker, H. Ainspan and M. Soyuer, IBM T. J. Watson Research Center, Yorktown Heights, NY |
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2:45 p.m. |
A 10-Gb/s CMOS Clock and Data Recovery Circuit, |
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10.4 |
J. Savoj and B. Razavi, University of California, Los Angeles, CA |
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3:10 p.m. |
Break |
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SESSION 11 - Tapa II Analog Techniques |
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Friday, June 16, 1:30 p.m. |
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Chairpersons: |
B. Razavi, UCLA, |
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1:30 p.m. |
A 50-mW 14-bit 2.5-MS/s x —@ Modulator in a 0.25[m Digital CMOS Technology, |
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11.1 |
P. Balmelli, Q. Huang and F. Piazza, Swiss Federal Inst. of Technology, Zurich, Switzerland |
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1:55 p.m. |
Linearization Method for Fast Voltage-to-Current Converters, |
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11.2 |
C. Paulus* and R. Thewes, Infineon Technologies AG, Munich, Germany and *Otto-von-Guericke University of Magdeburg, Magdeburg, Germany |
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2:20 p.m. |
A Variable Gain CMOS Amplifier with Exponential Gain Control, |
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11.3 |
C. Mangelsdorf, Analog Devices, Tokyo, Japan |
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2:45 p.m. |
A New Model for Thermal Channel Noise of Deep Submicron MOSFETs and its Application in RF-CMOS Design, |
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11.4 |
G. Knoblinger, P. Klein and M. Tiebout, Infineon Technologies AG, Munich, Germany |
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3:10 p.m. |
Break |
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SESSION 12 - Tapa III Flash Memories |
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Friday, June 16, 1:30 p.m. |
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Chairpersons: |
H. Pon, Intel Corp. |
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1:30 p.m. |
A Dual Page Programming Scheme for High-Speed Multi-Gb-Scale NAND Flash Memories, |
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12.1 |
K. Takeuchi and T. Tanaka, Toshiba Corp., Yokohama, Japan |
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1:55 p.m. |
1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications, |
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12.2 |
R. McPartland and R. Singh*, Bell Laboratories, Lucent Technologies, Allentown, PA and *Orlando, FL |
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2:20 p.m. |
A 60ns Access 32kByte 3-Transistor Flash for Low Power Embedded Applications, |
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12.3 |
T. Ikehashi, J. Noda, K. Imamiya, M. Ichikawa, A. Iwata and T. Futatsuyama, Toshiba Corporation, Yokohama, Japan |
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2:45 p.m. |
A Selective Verify Scheme for Achieving a 5-MB/s Program Rate in 3-bit/cell Flash Memories, |
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12.4 |
H. Kurata, N. Kobayashi, K. Kimura, S. Saeki* and T. Kawahara, Hitachi Ltd., Tokyo, Japan and *Hitachi Device Engineering Company Ltd., Chiba, Japan |
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3:10 p.m. |
Break |
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SESSION 13 - Tapa II High Speed Communications II |
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Friday, June 16, 3:25 p.m. |
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Chairpersons: |
B. Razavi, UCLA, |
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3:25 p.m. |
A Si BiCMOS Trans-Impedance Amplifier for 10Gb SONET Receiver, |
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13.1 |
H. H. Kim, S. Chandrasekhar, C. Burrows and J. Bauman, Bell Laboratories, Lucent Technologies, Holmdel, NJ |
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3:50 p.m. |
A 156 Mbps CMOS Laser Diode Driver for Optical Burst-Mode Transmission, |
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13.2 |
T. Matsuyama, M. Miki, T. Inoue*, N. Murakami and N. Ueno**, Fujitsu Hokkaido Digital Technology Ltd., Hokkaido, Japan and *Fujitsu Laboratories, Ltd., Kanagawa, Japan and **Fujitsu, Ltd., Kanagawa, Japan |
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4:15 p.m. |
A Constant Slew-Rate Ethernet Line Driver, |
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13.3 |
D. Nack, Level One Communications, Sacramento, CA |
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4:40 p.m. |
Analog Front End IC for Category I & II ADSL, |
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13.4 |
Guido, V. Leung, J. Kenney, J. Trackim, A. Agrillo, E. Zimany and R. Shariatdoust, Analog Devices, Inc., Somerset, NJ |
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SESSION 14 - Tapa III Microprocessor Circuits |
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Friday, June 16, 3:25 p.m. |
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Chairpersons: |
B. Gieseke, Advance Micro Devices, |
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3:25 p.m. |
A Clock Distribution Network for Microprocessors, |
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14.1 |
P. Restle, T. McNamara*, D. Webber*, P. Camporese*, K. Eng*, K. Jenkins, D. Allen**, M. Rohn**, M. Quaranta**, D. Boerstler#, C. Alpert#, C. Carter#, R. Bailey#, J. Petrovic#, B. Krauter# and B. McCredie#, IBM, Yorktown Heights and *Poughkeepsie, NY and **Rochester, MN and #Austin, TX |
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3:50 p.m. |
Comparative Delay, Noise and Energy of High-Performance Domino Adders with Stack Node Preconditioning (SNP), |
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14.2 |
Y. Ye, J. Tschanz, S. Narendra, S. Borkar, M. Stan* and V. De, Intel Corporation, Hillsboro, OR and *University of Virginia, Charlottesville, VA |
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4:15 p.m. |
470ps 64bit Parallel Binary Adder, |
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14.3 |
J. Park, H. Ngo*, J. Silberman* and S. Dhong*, Samsung Electronics, Kyoungki-Do, Korea and *IBM Austin Research Laboratory, Austin, TX |
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4:40 p.m. |
1 GHz Leading Zero Anticipator Using Independent Sign-Bit Determination Logic, |
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14.4 |
K. T. Lee and K. Nowka, IBM Austin Research Laboratory, Austin, TX |
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SESSION 15 - Tapa I Digital Circuit Techniques |
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Saturday, June 17, 8:30 a.m. |
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Chairpersons: |
J. Alvarez, Motorola, |
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8:30 a.m. |
A Low-Power Adiabatic Driver System for AMLCDs, |
15.1 |
R. Lal, W. Athas* and L. Svensson**, Advanced Bionics Corp., Sylmar, CA and *University of Southern California, Marina del Rey, CA and **Ericsson Mobile, Lund, Sweden |
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8:55 a.m. |
Level Converters with High Immunity to Power-Supply Bouncing for High-Speed Sub-1-V LSIs, |
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15.2 |
Y. Kanno, H. Mizuno, K. Tanaka and T. Watanabe, Hitachi, Ltd., Tokyo, Japan |
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9:20 a.m. |
VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem, |
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15.3 |
Y. Mitsuyama, Z. Andales, T. Onoye* and I. Shirakawa, Osaka University, Osaka, Japan and *Kyoto University, Kyoto, Japan |
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9:45 a.m. |
Break |
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SESSION 16 - Tapa II Nyquist Converters and Filters |
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Saturday, June 17, 8:30 a.m. |
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Chairpersons: |
L. McIlrath, Massachusetts Institute of Technology, |
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8:30 a.m. |
A 12b 105Msample/S, 850mW Analog to Digital Converter, |
16.1 |
C. Michalski, Analog Devices, Inc., Greensboro, NC |
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8:55 a.m. |
An 8-bit 125Ms/s CMOS Folding ADC for Gigabit Ethernet LSI, |
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16.2 |
K. Yoon, J. Lee, D.-K. Jeong and W. Kim, Seoul National University, Seoul, Korea |
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9:20 a.m. |
A 200MHz, 3mW, 16-Tap Mixed-Signal FIR Filter, |
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16.3 |
M. Figueroa and C. Diorio, University of Washington, Seattle, WA |
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9:45 a.m. |
An Adaptive Analog Noise-Predictive Decision-Feedback Equalizer, |
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16.4 |
M. Q. Le, P. Hurst and J. Keane, University of California, Davis, CA |
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10:10 a.m. |
Break |
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SESSION 17 - Tapa I Cache Memory |
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Saturday, June 17, 10:25 a.m. |
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Chairpersons: |
H. Pon, Intel Corp. |
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10:25 a.m. |
A 1.6 ns Access, 1 GHz Two-Way Set-Predicted and Sum-Indexed 64-kByte Data Cache, |
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17.1 |
J. Silberman, N. Aoki*, N. Kojima* and S. H. Dhong**, IBM T.J. Watson Research Center, Yorktown Heights, NY and * IBM Yasu Technology Applcation Laboratory, Shiga, Japan and **IBM Austin Research Laboratory, Austin, TX |
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10:50 a.m. |
A 2 GHz Cycle, 430 ps Access Time 34 Kb L1 Directory SRAM in 1.5 V, 0.18 [ m CMOS Bulk Technology, |
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17.2 |
R. Joshi, S. Kowalczyk, Y. Chan*, W. Huott*, S. Wilson* and G. Scharff*, IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY and *IBM System 390 Division, Poughkeepsie, NY |
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11:15 a.m. |
The Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-0.18 [ m Technologies, |
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17.3 |
K. Zhang, K. Hose, V. De and B. Senyk, Intel Corporation, Hillsboro, OR |
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11:40 a.m. |
A 16GB/s, 0.18 [ m Cache Tile for Integrated L2 Caches from 256KB to 2MB, |
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17.4 |
J. Miller, J. Conary and D. DiMarco, Intel Corporation, Hillsboro, OR |
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SESSION 18 - Tapa II Wireless Building Blocks II |
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Saturday, June 17, 10:25 a.m. |
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Chairpersons: |
L. McIlrath, Massachusetts Institute of Technology |
|
10:25 a.m. |
A 2-V 1.8-GHz Fully-Integrated CMOS Dual-Loop Frequency Synthesizer, |
|
18.1 |
T. K. Kan and H. Luong, Hong Kong University of Science and Technology, Kowloon, Hong Kong |
|
10:50 a.m. |
A 1.5-V 900-MHz Monolithic CMOS Fast-Switching Frequency Synthesizer for Wireless Applications, |
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18.2 |
C.-W. Lo and H.C. Luong, Hong Kong University of Science and Technology, Kowloon, Hong Kong |
|
11:15 a.m. |
A 1.8-GHz Self-Calibrated Phase-locked Loop with Precise I/Q Matching, |
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18.3 |
C.-H. Park, O. Kim* and B. Kim, KAIST, Taejon, Korea and *SK Telecom, Kyoungi-do, Korea |
|
11:40 a.m. |
A Very Low Power Channel Select Filter for IS-95 CDMA Receiver with On-Chip Tuning, |
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18.4 |
T. Kuo and B. Lusignan*, VLSI Technology, San Jose, CA and *Stanford University, Stanford, CA |
GENERAL INFORMATION
SCOPE OF SYMPOSIUM
The scope of the 2000 Symposium on VLSI Circuits covers all aspects of VLSI circuits, such as: circuits for digital, analog, memory, communications and signal processing applications, including A/D and D/A converters, mixed analog/digital functions and interface circuits; systems and architectures related to VLSI circuits; concepts in LSI's for system integration, for example MEMS; and fundamentals related to the above subjects, including innovative circuits and device structures.
REGISTRATION INFORMATION
The deadline to register is May 19, 2000. After May 19, 2000 you must register on-site. If you register on-site, an additional $75 will be added to the registration fees. Payment of the registration fee entitles the registrant to one copy of the Technical Digest, one CD-ROM, three Continental breakfasts, all coffee breaks, one banquet and one reception ticket.
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Member |
NonMember |
Students |
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US$ |
Yen |
US$ |
Yen |
US$ |
Yen |
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Technology Short Course |
$275 |
¥31000 |
$300 |
¥33000 |
$75 |
¥9000 |
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Statistical Metrology |
$185 |
¥21000 |
$225 |
¥25000 |
$175 |
¥20000 |
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Technology Symposium |
$395 |
¥45000 |
$445 |
¥50000 |
$195 |
¥22000 |
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Tech/Circuits Symposia |
$695 |
¥80000 |
$795 |
¥90000 |
$390 |
¥43000 |
|
Circuits Short Course |
$275 |
¥31000 |
$300 |
¥33000 |
$75 |
¥9000 |
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Circuits Symposium |
$395 |
¥45000 |
$445 |
¥50000 |
$195 |
¥22000 |
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Digests |
$75 |
¥9000 |
$75 |
¥9000 |
$75 |
¥9000 |
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Add'l Short CourseBook |
$40 |
¥5000 |
$40 |
¥5000 |
$40 |
¥5000 |
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Banquet Tickets |
$75 |
¥9000 |
$75 |
¥9000 |
$75 |
¥9000 |
Payment in US dollars is strongly encouraged by the use of credit cards (MasterCard/Visa) and through the American Secretariat. However, for special cases where payment in Japanese Yen is required, please remit your payment through the Japanese Secretariat.
REGISTRATION VIA AMERICAN SECRETARIAT
Credit Cards (MasterCard/Visa), personal checks, company checks or traveler’s checks payable to the 2000 VLSI Symposia in U.S. Dollars are the only acceptable forms of payment. All checks must be drawn on U.S. banks. Registration not conforming to these guidelines will be returned. Please complete the Registration Card (see centerfold) and return with payment of the appropriate registration fees no later than May 19, 2000 to Widerkehr and Associates, 101 Lakeforest Boulevard, Suite 400B, Gaithersburg, MD 20877 USA.
REGISTRATION VIA JAPANESE SECRETARIAT
Bank drafts, bank transfers and company checks payable to the VLSI Symposia in Japanese Yen are the only acceptable forms of payment. Personal checks and credit cards will NOT be accepted. Please complete the Registration Card (see centerfold) and return with payment of the appropriate registration fees NO LATER THAN MAY 19, 2000 to the Business Center for Academic Societies Japan, Conference Dept., 5-16-9 Honkomagome, Bunkyo-ku, Tokyo 113-8622, Japan.
CANCELLATION POLICY
All requests for refunds for registrations paid in US dollars must be made in writing and submitted to Widerkehr and Associates, 101 Lakeforest Boulevard, Suite 400B, Gaithersburg, MD 20877 USA. All requests for refunds for registrations paid in Japanese Yen also must be made in writing and submitted to the Business Center for Academic Societies Japan, 5-16-9 Honkomagome, Bunkyo-ku, Tokyo 113-8622, Japan. Refunds, minus a $30.00 or ¥3300 processing fee, will be issued for cancellations received on or before May 26, 2000. No refunds will be issued for cancellations received after May 26, 2000. All refunds will be processed after the Symposia.
SYMPOSIA COORDINATION CENTER
The Symposia Coordination Center, located in the Palace Lounge Lobby will be open as follows:
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Symposium on VLSI Circuits |
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Wednesday, June 14 |
7:30 am - 5:00 pm |
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Thursday, June 15 |
7:30 am - 5:00 pm |
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Friday, June 16 |
8:00 am - 5:00 pm |
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Saturday, June 17 |
8:00 am - 12:00 noon |
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Symposium on VLSI Technology |
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Sunday, June 11 |
5:00 pm - 8:00 pm |
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Monday, June 12 |
7:30 am - 5:00 pm |
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Tuesday, June 13 |
7:30 am - 5:00 pm |
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Wednesday, June 14 |
7:30 am - 5:00 pm |
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Thursday, June 15 |
7:30 am - 5:00 pm |
VLSI CIRCUITS SYMPOSIUM RECEPTION
A reception will be held on Wednesday, June 14 from 7:00 pm to 9:00 pm on the Village Green.
VLSI CIRCUITS SYMPOSIUM BANQUET
The 2000 Symposium on VLSI Technology Banquet will be held on Friday, June 16 on the Lagoon Green from 7:00 pm to 9:00 pm. Banquet tickets for accompanying guests can be purchased at the Registration desk in the Palace Lounge Lobby.
SPEAKER PREPARATION CENTER
There will be a designated Speaker Preparation Room. Specifics will be available at the Registration Desk located in the Palace Lounge Lobby.
TECHNICAL DIGEST
Registrants will receive (1) copy of the Technical Digest and (1) copy of the CD-Rom when they pick up their Symposium materials at the Registration Desk. Additional copies of the Technical Digest will be available on-site for $75/Digest. Following the Symposium, additional copies of the Technical Digest will be available through IEEE Single Copy Sales, 445 Hoes Lane, Piscataway, NJ 08855, USA (Toll free) 1-800-678-4333.
TRAVEL EXPENSE SUPPORT
Requests for partial travel expense support for students who are presenting papers should be sent to: David Scott, Texas Instruments, 13560 N. Central Expressway, P.O. Box 650311, MS 3735, Dallas, TX, no later than April 26, 2000. All travel support will be paid after the Symposia.
MESSAGE CENTER
The Message Board will be located in the Palace Lounge Lobby adjacent to the Registration Desk. Please advise those who wish to reach you during the day to contact the Hilton Hawaiian Village at 808-949-4321 and request the VLSI Symposia Message Desk. Facsimiles clearly marked with both the recipient's name and the name of the Symposia may be sent to 808-947-7914. Please check the Message Board regularly, since there will be no delivery service provided.
GUEST ORIENTATION
A guest orientation with continental breakfast will be held at 9:00 a.m., Thursday, June 15 in the Iolani IV room. Sightseeing information will be provided.
STATISTICAL METROLOGY WORKSHOP
The Fifth International Workshop on Statistical Metrology will be held on Sunday, June 11, 2000 in Honolulu, Hawaii. The Workshop will be held in association with and precede the 2000 Symposium on VLSI Technology. This Workshop is an opportunity to learn about state of the art statistical methods for the design of VLSI process, devices, and circuits. This year’s agenda features a keynote address by Prof. Tadahiro Ohmi, "Perfect Scientific Manufacturing Free from Fluctuations" and three tutorial talks by leading workers in the field. The talks will be Dr. Steve Duvall, Intel, on statistical circuit modeling; Dr. Sani Nassif, IBM, on statistical process models; and Dr. Andrzej Strojwas, PDF Solutions, on yield modeling.
For the first time, this one-day Workshop integrates tutorials with the technical sessions in order to (1) raise process, device and circuit designer’s awareness about variation and statistical issues in design; and (2) provide a forum for discussion among researchers working in this field. The final program will be available on the web by March 31, 2000 at:
http://www-mtl.mit.edu/StatMet2000/
To obtain an Advance Program and other general information or to be placed on the Symposia mailing list, please contact:
2000 Symposia on VLSI Technology and Circuits
Widerkehr and Associates
101 Lakeforest Boulevard, Suite 400B
Gaithersburg, MD 20877 USA
Phone: +1-301-527-0900 Fax: +1-301-527-0994.
Email: vlsi00@aol.com
2000 VLSI CIRCUITS SYMPOSIUM COMMITTEE
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Chairman: |
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William Bidermann |
S3 Incorp. |
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Co-Chairman: |
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Takayasu Sakurai |
University of Tokyo |
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Program Chairman: |
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David Scott |
Texas Instruments |
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Program Co-Chairman: |
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Masakazu Yamashina |
NEC Corp. |
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Secretary: |
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Shekhar Borkar |
Intel Corp. |
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Tadahiro Kuroda |
Toshiba Corp. |
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Publications: |
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Wah Kit Loh |
Texas Instruments |
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Masato Motomura |
NEC Corp. |
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Publicity: |
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Wah Kit Loh |
Texas Instruments |
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Tadahiro Kuroda |
Toshiba Corp. |
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Treasurer: |
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Richard Jaeger |
Auburn University |
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Shinji Odanaka |
Matsushita Semiconductor |
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Local Arrangements: |
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Yuan Taur |
IBM Research Center |
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Hiroshi Hanafusa |
Sanyo Electric |
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Kazunori Nakahara |
Sharp Corp. |
EXECUTIVE COMMITTEES
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IEEE Chairman: |
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James T. Clemens |
Bell Labs, Lucent Technologies |
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Members: |
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Asad Abidi |
UCLA |
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Antonio Alvarez |
Cypress Semiconductor |
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Bill Bidermann |
S3 Inc. |
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Gilbert DeClerck |
IMEC |
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Youssef El-Mansy |
Intel Corporation |
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Richard Jaeger |
Auburn University |
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Nino Masnari |
North Carolina State Univ. |
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Yoshi Nishi |
Texas Instruments |
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Kevin O'Connor |
Bell Labs, Lucent Technologies |
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Bill Siu |
Intel Corp. |
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Charles Sodini |
Massachusetts Institute of Technology |
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Peter Verhofstadt |
Semiconductor Research Corporation |
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Ian Young |
Intel Corp. |
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JSAP Chairman: |
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Takuo Sugano |
Toyo University |
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Co-Chairman: |
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Susumu Kohyama |
Toshiba |
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Members: |
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Chun-Yen Chang |
National Chiao Tung University |
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Masao Fukuma |
NEC |
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Yutaka Hayashi |
University of Tsukuba |
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Koichiro Hoh |
University of Tokyo |
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Chang-Gyu Hwang |
Samsung Electronics |
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Hajime Ishikawa |
Fujitsu Laboratories |
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Atsushi Iwata |
Hiroshima University |
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Masakazu Kakumu |
Toshiba |
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Choong-Ki Kim |
KAIST |
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Yojiro Mano |
Matsushita Electric |
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Toshiaki Masuhara |
Hitachi |
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Akihiko Morino |
NEC |
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Tadashi Nishimura |
Mitsubishi Electric |
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Tsunenori Sakamoto |
Electrotechnical Laboratory |
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Takayasu Sakurai |
University of Tokyo |
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Masao Taguchi |
Fujitsu |
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Eiji Takeda |
Hitachi |
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Ken Takeya |
NTT |
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Fang-Churng Tseng |
TSMC |
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Masakazu Yamashina |
NEC |
TECHNICAL PROGRAM COMMITTEES
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NORTH AMERICA/EUROPE |
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Chairman: |
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David Scott |
Texas Instruments |
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Members: |
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Asad Abidi |
University of California |
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Jose Alvarez |
IBM |
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Shekhar Borkar |
Intel Corp. |
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Bernhard Boser |
UC Berkeley |
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William Carter |
Xilinx, Inc. |
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Anantha Chandrakasan |
MIT |
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Ching-Te Chuang |
IBM |
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Larry DeVito |
Analog Devices |
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Bruce Gieseke |
AMD |
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Peter Gillingham |
MOSAID |
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Paul Gray |
University of California |
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Tord Haulin |
Ericsson Telecom AB |
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Mark Horowitz |
Stanford University |
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Richard Jaeger |
Auburn University |
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Wah Kit Loh |
Texas Instruments |
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Niles Kynett |
Intel Corp. |
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Wai Lee |
Texas Instruments |
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Lisa McIlrath |
MIT |
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Gitty Nasserbakht |
Proxim, Inc. |
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Behzad Razavi |
UCLA |
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Greg Taylor |
Intel Corp. |
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Jacob White |
MIT Research Laboratory for Electronics |
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JAPAN/FAR EAST |
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Co-Chairman: |
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Masakazu Yamashina |
NEC Corp. |
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Members: |
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Mitsuru Hiraki |
Hitachi |
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Akira Hyogo |
Science University of Tokyo |
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Makoto Ikeda |
University of Tokyo |
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Deog-Kyoon Jeong |
Seoul National University |
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Takahiro Kamei |
Oki Electric |
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Masayuki Katakura |
Sony Corp. |
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Changhyun Kim |
Samsung Electronics |
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Kazutoshi Kobayashi |
Kyoto University |
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Koji Kotani |
Tohoku University |
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Nicky C.C. Lu |
Etron Technology |
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Masataka Matsui |
Toshiba Corp. |
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Takahiro Miki |
Mitsubishi Electric |
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Toshihiko Mori |
Fujitsu Labs |
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Masato Motomura |
NEC Corp. |
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Kazunori Nakahara |
Sharp Corp. |
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Yusuke Ohtomo |
NTT |
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Atsushi Wada |
Sanyo Electric |
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Hiroyuki Yamauchi |
Matsushita Electric |